Shift Register Simulator
Shift left/right and watch data go serial-in parallel-out, or parallel-in serial-out.
What it does: Interactively demonstrate a shift register: feed in serially or load in parallel, shifting all bits by one each clock.
When to use it: When learning the 74HC595/165, understanding serial/parallel conversion, or doing IO expansion.
0 = 00000000 MEANS —
No history yet. Each calculation is automatically saved to this device.
How to use the shift register simulator
Set width and direction → serial in / parallel load → clock to watch the shift.
- 01
Set the width and direction
Width (e.g. 8 for a 74HC595), shift left or right. Serial data enters one end and leaves the other.
- 02
Serial in: set the input bit + clock
Click the serial input bit to set 0/1, then press "Clock ↑" to shift one bit in — this is the SIPO (serial-in, parallel-out) process.
- 03
Parallel-in, serial-out (PISO)
Enter a value and click "Parallel load" to load the whole group into the register, then keep clocking and watch the data shift out serially bit by bit from the other end.
Three usage modes
Same shift register, classified by how data goes in / comes out.
| Mode | In | Out | Typical chip |
|---|---|---|---|
| SISO | Serial | Serial | Delay line |
| SIPO | Serial | Parallel | 74HC595 (serial-to-parallel) |
| PISO | Parallel load | Serial | 74HC165 (parallel-to-serial) |
Standard shift register operating modes.
Common questions, answered in 3 minutes
Which type is the 74HC595?
SIPO (serial-in, parallel-out): feed in 8 bits serially over 3 wires, then output them in parallel to 8 pins — commonly used to expand IO or drive 7-segment displays / LED arrays.
How do I choose shift left vs. right?
It depends on which end data enters. In this tool, shift right = data enters at the left and exits at the right; shift left is the reverse. First be clear about "where the first-sent bit ends up".
Why does sending N bits serially take N clocks?
Each clock shifts in only one bit, so an N-bit register needs N clocks to fully load a group of data (SIPO) or fully output it (PISO).
Where do the shifted-out bits go?
They are lost after leaving the end (or chained to the next register stage). This tool records each clock's shifted-out bit in the history so you can watch the PISO serial output.
How is this different from a counter?
A counter increments/decrements according to a pattern; a shift register just slides the existing bits over as a whole, one bit in / one bit out, doing no arithmetic itself.
Standards and sources referenced by this tool
| Item | Value / Formula | Source |
|---|---|---|
| Shift operation | Slide all bits by one | Digital logic standard |
| Operating modes | SISO/SIPO/PISO | shift register modes |
Ideal next-state model, excludes latch/enable timing, no external API.