Logic Level Voltage Reference
Quick reference of voltage thresholds for each logic family + a cross-level direct-connect check.
What it does: Look up the high/low level thresholds of TTL/CMOS/LVCMOS and decide whether two chips can connect directly.
When to use it: When mixing 5V and 3.3V devices, troubleshooting unrecognized levels, or choosing whether level shifting is needed.
Pick a driver and a receiver to decide whether the output can reliably drive the input; the noise margins? are safe only when both are positive.
⚠ Over-voltage risk: the driver supply is higher than the receiver, so the 5V signal may damage non-5V-tolerant pins — level shifting or confirmed 5V tolerance is required.
MEANS —
No history yet. Each calculation is automatically saved to this device.
How to use the logic level reference
Check thresholds → pick driver/receiver → read the direct-connect verdict.
- 01
Check the threshold table
The table below lists VIL/VIH (input thresholds) and VOL/VOH (output thresholds) for each logic family. Between VIL and VIH is the forbidden region, where the level is undefined.
- 02
Pick driver → receiver
In the "interconnect check" select the output chip and input chip to instantly see whether they can connect directly, and whether there is an over-voltage risk.
- 03
Read the verdict and margins
Both the high and low level margins must be > 0 for a reliable direct connection; if the driver rail is higher, it will warn that level shifting or 5V tolerance is needed.
Logic family level thresholds (V)
VIL/VIH = input low/high thresholds; VOL/VOH = guaranteed output low/high values (at rated load).
| Logic family | VCC | VIL≤ | VIH≥ | VOL≤ | VOH≥ |
|---|---|---|---|---|---|
| TTL (74xx / 74LS) | 5V | 0.8 | 2 | 0.4 | 2.4 |
| 5V CMOS (74HC, 4000B) | 5V | 1.5 | 3.5 | 0.1 | 4.4 |
| 5V CMOS-TTL (74HCT) | 5V | 0.8 | 2 | 0.1 | 4.4 |
| LVTTL (3.3V) | 3.3V | 0.8 | 2 | 0.4 | 2.4 |
| LVCMOS 3.3V | 3.3V | 0.8 | 2 | 0.4 | 2.4 |
| LVCMOS 2.5V | 2.5V | 0.7 | 1.7 | 0.4 | 2 |
| LVCMOS 1.8V | 1.8V | 0.63 | 1.17 | 0.45 | 1.35 |
Common TTL/74HC(T) datasheet values + JEDEC JESD8-A/8-5/8-7 (2.5/1.8V output thresholds vary with load).
Common questions, answered in 3 minutes
Can a 3.3V MCU directly drive a 5V chip?
It depends on the receiver. Most 5V CMOS (74HC) require VIH≥3.5V, but a 3.3V device only guarantees a high level of about 2.4–3.3V, which may not be enough — in that case switch to TTL-input-compatible 74HCT, or add level shifting. This tool's interconnect check gives the verdict directly.
Is connecting a 5V output to a 3.3V input safe?
The levels are fine (a 5V high level far exceeds the VIH of a 3.3V device), but 5V may exceed the voltage rating of the 3.3V device and damage the pin — unless that pin is marked 5V tolerant. The tool warns about over-voltage risk.
What does "forbidden region / undefined" mean?
For a voltage between VIL and VIH, the chip guarantees neither a low nor a high reading and may misread or oscillate. In your design, keep the signal firmly outside the thresholds.
How is noise margin calculated?
High-level margin = VOH − VIH, low-level margin = VIL − VOL. The larger the margin, the better the noise immunity.
Why do 74HC and 74HCT have different thresholds?
74HC uses pure CMOS thresholds (0.3/0.7·VCC); 74HCT deliberately makes the input thresholds TTL-compatible (0.8/2.0V) to make it easy to receive TTL or 3.3V signals.
Standards and sources referenced by this tool
| Item | Value / Formula | Source |
|---|---|---|
| TTL / 74HC(T) | 0.8/2.0 · 1.5/3.5 | Standard logic datasheets |
| LVTTL / LVCMOS | JESD8-A / 8-5 / 8-7 | JEDEC |
Thresholds are nominal values at rated load; 2.5/1.8V output thresholds vary with load — for precise design, refer to the datasheet as authoritative.